Such devices are known from US patent publication US2008/0183949, which describes a method for programming a flash memory. Programming within this context is understood by a person skilled in the art as writing or storing bits in the flash memory cells. Programming data on a flash memory is done by programming data of one page at one time. If not enough data is provided at the end of the data stream to program a full page, the page programmed at the end of the data stream is only partially filled. If the data stream to be programmed continues later on, there is a partially filled page between other fully filled pages. This can be regarded as insufficient. A better solution is provided by reading out again the partially filled data page and completing the data with data later provided to be written and then programming a full data page to the flash memory. Partially filled pages are reduced at the cost of additional read and programming cycles.
US patent publication US2006/0136656 describes a block as the minimum erasable unit of a flash memory. It further describes the problem of partially filled pages which cannot be erased easily because the minimum erasable unit is not a page but a block. Thus, the flash memory is worn down unnecessarily.
The effect of partially filled pages also arises when a switching operation between two logical units is performed. When a switch from a first logical unit to a second logical unit is performed, the data left in an input buffer is programmed to the first logical unit and after that the switching to the second logical unit is made. If later on data are programmed to the first logical unit, a new page is used for programming the data and thus, partially used pages arise in the logical unit.
According to the Open NAND Flash Interface Specification (ONFI), writing data to a NAND Flash device is done by issuing a PROGRAM PAGE command with the corresponding logical unit number (LUN), block address and page address to the target. Afterwards data of a complete memory page, usually multiple kilobytes, is written to the page register of the selected logical unit. When a full page is written to the page register, the logical unit starts to program the data to its memory array. During programming, the logical unit is busy and the next page can be written to the logical units' page register after programming of the first page is finished. After a complete page has been written to the page register and the page program has been started, the other logical units of the target could be selected and used. The ONFI specification provides also a possibility to program partial pages, but that would implicate additional programming times and the reachable bandwidth would decrease.
The following programming instructions are defined according to the ONFI specification:                PAGE PROGRAM: Data is written to the data register and programming starts after the data phase has finished.        PAGE CACHE PROGRAM: Data is written to the data register and after the data phase is finished, the content of the data register is copied to the cache register and programming starts.        PAGE PROGRAM INTERLEAVED: Data is written to multiple data registers of one LUN and programming starts when the last data register is filled.        
The known page program flow is used to write a complete data page to the page register of the NAND device and to start the programming to the memory array. Each procedure causes a number of state switches of the target state machine and the logical unit state machine. The state switches of the state machines in dependence of the procedure are shown below:
ProcedureTarget State SequenceLUN State SequenceWrite Command 80hT_IdleL_Idleto NAND device−> T_Cmd_Decode−> T_PP_Execute−> T_PP_AddrWaitWrite LUN-, block-T_PP_AddrWaitL_Idleand page-address−> T_PP_Addr−>L_Idle_TargetRequestto NAND device−> T_PP_LUN_Execute −> L_ PP Execute−> T_PP_LUN_DataWait−> L_PP_Addr−> L_PP_WaitForDataWrite completeT_PP_LUN_DataWaitL_PP_WaitForDatadata page to NAND−> T_PP_LUN_ DataPass−> L_PP_AcceptDatadevice−> T_PP_LUN DataWait−> L_PP_WaitForDataWrite Command 10hT_PP_LUN_DataWaitL_PP_WaitForDatato NAND device−> T_PP_Cmd_Pass−> L_PP_Prog−> T_Idle−> L_PP_ProgWait−> L_PP_Sts−> L_Idle
Interleaved operations enable to issue multiple commands of the same type to different blocks of the same logical unit. The known interleaved page program flow is used to write complete data pages to multiple independent page registers of a logical unit and to start the programming to the memory array when all registers are filled.
ProcedureTarget State Sequence LUN State SequenceWrite Command T_IdleL_Idle80h to NAND −> T_Cmd_Decodedevice−> T_PP_Execute−> T_PP_AddrWaitWrite LUN-, block- T_PP_AddrWaitL_Idleand page-address−> T_PP_Addr−> L_Idle_TargetRequestto NAND device−> T_PP_LUN_Execute−> L_PP_Execute−> T_PP_LUN_DataWait−> L_PP_Addr−> L_PP_WaitForDataWrite completeT_PP_LUN_DataWaitL_PP_WaitForDatadata page to −> T_PP_LUN_DataPass−> L_PP_AcceptDataNAND device−> T_PP_LUN_DataWait−> L_PP_WaitForDataWrite Command T_PP_LUN_DataWaitL_PP_WaitForData11h to NAND −> T_PP_Cmd_Pass−> L_PP_Ilvdevice−> T_PP_IlvWait−> L_PP_Ilv_WaitWrite Command T_PP_IlvWaitL_PP_Ilv_Wait80h* to NAND −> T_PP_AddrWaitdeviceWrite LUN-, block-T_PP_AddrWaitL_PP_Ilv_Waitand page-address−> T_PP_Addr−> L_PP_Addrto NAND device−> T_PP_LUN_Execute−> L_PP_WaitForData−> T_PP_LUN_DataWaitWrite completeT_PP_LUN_DataWaitL_PP_WaitForDatadata page to NAND−> T_PP_LUN_DataPass−> L_PP_AcceptDatadevice−> T_PP_LUN_DataWait−> L_PP_WaitForDataWrite Command T_PP_LUN_DataWaitL_PP_WaitForData10h to NAND −> T_PP_Cmd_Pass−> L_PP_Progdevice−> T_Idle−> L_PP_ProgWait−> L_PP_Sts−> L_Idle*The address cycles for the program operation of state ‘T_PP_IlvWait’ is intended to have a different interleaved block address than the one issued in the preceding program operation.
If data of two independent sources are recorded in independent LUNs of a target, one of the above described processes is first issued to the first LUN for the first independent source and after finishing the writing process, one of the above described processes is issued to the second LUN for writing the data of the second independent source to the second LUN.
When independent concurrent streams should be recorded to a flash device, it is advantageous to write the different streams to different logical units. The file management is easier with such a regular strategy and the full bandwidth of a logical unit is guaranteed for recording of an incoming data stream. If data of the streams arrive in blocks of smaller size than the page size, there is a need to cache data of each stream in a cache arranged outside of the flash device and to write it to the NAND Flash device, when a full page for one logical unit is ready to be programmed. Depending on the amount of streams and logical units, a lot of cache memory is needed outside the memory device, while the available page register inside the device remains unused.